In a semiconductor device including a high withstand voltage semiconductor element, a plurality of pn junction structures are formed in a semiconductor substrate including a silicon substrate. When a pnp junction structures are formed, an n-type region is formed by injecting n-type impurities into the surface of a p-type silicon substrate. Then, a p-type region (an epitaxial layer) is formed using an epitaxial growth method, on the surface of its n-type region.
An element region is defined on the p-type region. In the element region, a high withstand voltage semiconductor element, such as an n-channel type high withstand voltage MOS transistor, is formed. The element region is defined by forming an element isolation region in a predetermined region in the p-type region which has been formed using the epitaxial growth method.
To form the element isolation region in the p-type region, a mark for superposition inspection is formed in advance, on the surface of the silicon substrate. By detecting this mark and a photoresist pattern, it is determined whether a desired photoresist pattern for forming the element isolation region has been formed in a predetermined position relative to the base pattern.
This mark is applied to a determination as to whether a desired photoresist pattern has been formed, at the time when, for example, a drain region of a high withstand voltage element is formed in the p-type region. This type of semiconductor device is disclosed in Japanese Unexamined Patent Application Publication No. 2008-16639.